Full-time
Chip Design
Digital IC Design Engineer / Senior / Principal
Responsible for RTL design, synthesis and timing closure, and participation in SoC system integration.
Responsibilities
- 负责数字模块的 RTL 设计、功能仿真与综合实现
- 参与 SOC 系统架构定义、总线互联与低功耗设计
- 配合验证团队完成模块与系统级验证，收敛时序与面积
- 支持流片后硅验证与问题调试
Requirements
- 微电子、集成电路、电子工程等相关专业本科及以上学历
- 熟悉 Verilog/SystemVerilog 与数字前端设计流程
- 理解时钟复位、低功耗、DFT 等基本设计约束
- 有以下经验者优先：MCU 内核集成、通信接口（LIN/CAN/SPI/I2C）、电机控制硬件加速
- 具备良好的沟通协作能力与文档习惯
What we offer
- 有市场竞争力的薪酬，含绩效奖金与股权激励
- 五险一金 + 补充商业医疗保险
- 与资深车规芯片专家共事，参与从定义到量产的完整流程
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