Full-time
Verification & Test
Digital Verification Engineer / Senior / Principal
Responsible for block-level and SoC-level verification and for building reusable verification platforms.
Responsibilities
- 制定验证计划，搭建与维护模块级 / 系统级验证环境
- 基于 UVM 等方法学开发测试用例，完成覆盖率收敛
- 负责形式验证、低功耗验证与门级后仿
- 参与硅后问题复现与调试
Requirements
- 微电子、集成电路、计算机等相关专业本科及以上学历
- 熟悉 SystemVerilog 与 UVM 验证方法学
- 熟悉脚本语言（Python / Perl / Shell）者优先
- 有车规芯片验证经验者优先
- 具备良好的问题定位能力与文档习惯
What we offer
- 有市场竞争力的薪酬，含绩效奖金与股权激励
- 五险一金 + 补充商业医疗保险
- 与资深车规芯片专家共事，参与从定义到量产的完整流程
Other open positions
Need selection support or samples?
Our application engineers work from your system design and provide magnet selection, field simulation, motor system support and reference designs.